v 20050820 1 L 300 0 300 600 3 0 0 0 -1 -1 L 300 600 700 600 3 0 0 0 -1 -1 T 300 -200 5 10 0 1 0 0 1 device=7400 T 500 900 5 10 0 0 0 0 1 slot=1 T 500 1100 5 10 0 0 0 0 1 numslots=4 T 500 1300 5 10 0 0 0 0 1 slotdef=1:1,2,3 T 500 1500 5 10 0 0 0 0 1 slotdef=2:4,5,6 T 500 1700 5 10 0 0 0 0 1 slotdef=3:9,10,8 T 500 1900 5 10 0 0 0 0 1 slotdef=4:12,13,11 L 300 0 700 0 3 0 0 0 -1 -1 A 700 300 300 270 180 3 0 0 0 -1 -1 V 1050 300 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 P 1100 300 1300 300 1 0 1 { T 1100 350 5 8 1 1 0 0 1 pinnumber=3 T 1100 250 5 8 0 1 0 2 1 pinseq=3 T 950 300 9 8 0 1 0 6 1 pinlabel=Y T 950 300 5 8 0 1 0 8 1 pintype=out } P 300 100 0 100 1 0 1 { T 200 150 5 8 1 1 0 6 1 pinnumber=2 T 200 50 5 8 0 1 0 8 1 pinseq=2 T 350 100 9 8 0 1 0 0 1 pinlabel=B T 350 100 5 8 0 1 0 2 1 pintype=in } P 300 500 0 500 1 0 1 { T 200 550 5 8 1 1 0 6 1 pinnumber=1 T 200 450 5 8 0 1 0 8 1 pinseq=1 T 350 500 9 8 0 1 0 0 1 pinlabel=A T 350 500 5 8 0 1 0 2 1 pintype=in } T 300 700 8 10 1 1 0 0 1 refdes=U? T 500 2050 5 10 0 0 0 0 1 footprint=so14_tbl T 500 2250 5 10 0 0 0 0 1 description=4 NAND gates with 2 inputs T 500 2450 5 10 0 0 0 0 1 documentation=http://www-s.ti.com/sc/ds/sn74hc00.pdf